FIG. 1 is a block diagram showing the configuration of a related ring oscillator. A ring oscillator may be made up of a plurality of delay chains 102 to 103. As shown in FIG. 1, one delay chain 102 has a NAND gate 101, and a chain of inverters IV-1 to IV-N. That is, the delay chain 102 includes a NAND gate 101, a first inverter IV-1 having an input connected to the output of the NAND gate 101, and a second inverter IV-2 having an input connected to the output of the first inverter IV-1. In this manner, the inverters IV-1 to IV-N are sequentially connected up to the Nth inverter IV-N to constitute a chain structure. The output of the Nth inverter IV-N is fed back to an input of the NAND gate 101 at the same time it is externally outputted. A delay chain 103 is additionally provided, which may be of any standard cell type.
The ring oscillator with the above configuration outputs pulses 104A and 104B, each having a certain period. Each output pulse 104A or 104B has a width corresponding to the sum of propagation delay times of standard cells constituting the delay chains 102 to 103 of the ring oscillator. A low to high delay time of each of the standard cells constituting the ring oscillator is obtained by measuring the width of each pulse 104A or 104B through an oscilloscope and multiplying the measured width by a low to high delay time ratio in SPICE.
FIG. 2 is a block diagram showing the configuration of a related digital process monitor circuit. Referring to FIG. 2, the related digital process monitor circuit includes a ring oscillator 201, an asynchronous ripple counter 202, a local counter 203, and a register interface and control unit 205. The register interface and control unit 205 receives an external clock signal CLK, a start command DPM_START and a test cycle period DPM_COUNT_DOWN and outputs a test end signal DPM_DONE, and a count value DPM_COUNT generated by the asynchronous ripple counter 202.
Upon receiving the start command DPM_START, the register interface and control unit 205 outputs, to the ring oscillator 201, an enable signal ENABLE to start the operation of the ring oscillator 201. Upon receiving the enable signal ENABLE, the ring oscillator 201 generates a clock pulse RING_OSC_CLK 204 and transfers it to the asynchronous ripple counter 202 and the register interface and control unit 205. The asynchronous ripple counter 202 counts down in response to the clock pulse RING_OSC_CLK 204.
While the start command DPM_START is applied to the register interface and control unit 205, the local counter 302 receives the test cycle period DPM_COUNT_DOWN from the register interface and control unit 205. After receiving the test cycle period DPM_COUNT_DOWN, the local counter 203 counts down by 2DPM—COUNT—DOWN (in other words, two raised to the power of the value of DPM_COUNT_DOWN).
When the value of the local counter 203 reaches 0, the local counter 203 transfers the test end signal DPM_DONE to the register interface and control unit 205. Upon receiving the test end signal DPM_DONE, the register interface and control unit 205 stops the entire circuit operation. At this time, the asynchronous ripple counter 202 generates the count value DPM_COUNT and transfers it to the register interface and control unit 205. Then, the register interface and control unit 205 outputs the count value DPM_COUNT transferred from the asynchronous ripple counter 202. Lastly, the asynchronous ripple counter 202 is initialized by a reset signal RESET from the register interface and control unit 205. At this time, the ring oscillator 201 is stopped by a synchronization stop signal SYNC_STOP from the register interface and control unit 205. The period of the clock pulse 204 from the ring oscillator 201 is measured using the count value DPM_COUNT outputted from the register interface and control unit 205.
FIG. 3 is a block diagram showing the configuration of a related apparatus for measuring the speed of a ring oscillator. Referring to FIG. 3, the related ring oscillator speed measurement apparatus includes a ring oscillator 316, a ring counter 307, an enable controller EN 308, a system counter 311, and a count detector 312.
The ring oscillator 316 includes an AND gate 302 and a plurality of inverters 303 to 305 connected in series. The output of the last inverter 305 is positively fed back to the AND gate 302.
The ring oscillator 316 generates a clock pulse RING CLK 306 and outputs it to the ring counter 307. The period of the clock pulse RING CLK 306 is determined depending on a propagation delay time from the AND gate 302 to the last inverter 305. As a result, the period of the clock pulse RING CLK 306 is in proportion to the number of inverters used. The clock pulse RING CLK 306 may have a maximum or minimum frequency under the influence of a process, temperature or voltage variation. The clock pulse RING CLK 306 is inputted to the ring counter 307. The ring counter 307 is a down counter that performs down counting. This ring counter 307 decrements a first preset value at every period of the inputted clock pulse RING CLK 306.
The AND gate 302 of the ring oscillator 316 is concerned in activation of the ring oscillator 316. That is, when the output of the AND gate 302 is “1”, the ring oscillator 316 generates the clock pulse 306 continuously. In other words, the ring oscillator 316 provides a rising edge pulse such that the ring counter 307 counts down. When the clock pulse RING CLK 306 is “1”, the output of the enable controller EN 308 is “1” and a disable shift value DISABLE-SHIFT is “1”, the AND gate 302 outputs “1”.
The disable shift value DISABLE-SHIFT is a value inputted from a test device, which acts to block a test vector or logic value for a test while the apparatus of FIG. 3 measures the speed of the ring oscillator 316. Also, the disable shift value DISABLE-SHIFT functions to stop the down counting for a period between a time at which a shift is ended and a time at which the output of the enable controller EN 308 is changed to “1”.
The enable controller EN 308 provides an enable signal ENABLE to the system counter 311. Also, this enable signal ENABLE controls activations of the ring oscillator 316 and system counter 311 together with the aforementioned disable shift value DISABLE-SHIFT. When the enable signal ENABLE from the enable controller EN 308 is “0”, the oscillation of the ring oscillator 316 and the operation of the system counter 311 are stopped. The enable controller EN 308 is composed of one D flip-flop. The enable controller EN 308 receives the output of the count detector COUNT DET 312 and outputs the enable signal ENABLE to the AND gate 302 and the system counter 311 synchronously with a system clock pulse SYS CLK 310.
The system counter 311 is enabled in response to the enable signal ENABLE from the enable controller EN 308 to decrement a second preset value at every period of the system clock pulse SYS CLK 310 synchronously with the system clock pulse SYS CLK 310. The system counter 311 outputs the decremented second preset value to the count detector COUNT DET 312. The count detector COUNT DET 312 detects the second preset value inputted from the system counter 311.
In detail, the count detector COUNT DET 312 detects when the second preset value inputted from the system counter 311 is “0” or “1”, and outputs “0” to the enable controller EN 308 as a result of the detection. Upon receiving “0” from the count detector COUNT DET 312, the enable controller EN 308 outputs the enable signal ENABLE of “0” to the AND gate 302 and the system counter 311 to stop the oscillation of the ring oscillator 316 and the operation of the system counter 311.
When the ring oscillator 316 is stopped as mentioned above, the ring counter 307 outputs a count value 315 obtained by periodically decrementing the first preset value. The count value 315, the second preset value and the period of the system clock pulse SYS CLK 310 are used as factors for measurement of the speed of the ring oscillator 316.
In the above-mentioned related measurement apparatus, in order to calculate a propagation delay time of a standard cell, it is necessary to measure the width of the clock pulse outputted from the ring oscillator. This means that the measurement must be made at the oscilloscope or wafer stage. For this reason, high-performance equipment and much manpower and time are required. Further, the process of measuring the width of the clock pulse outputted from the ring oscillator may be subject to the human error of the measurer or an internal error of the equipment, resulting in difficulties with measurement accuracy.
FIG. 4 is a graph illustrating an error in measurement for calculation of a propagation delay time of a standard cell by the related measurement apparatus. In this drawing, SYS CLK denotes a system clock pulse, EN denotes an enable signal for ON/OFF control of a ring oscillator, RING CLK denotes an output pulse from the ring oscillator, Counter′ denotes an output count value from a ring counter having an error, and Counter″ denotes a reference count value.
In FIG. 4, because the application time of the second enable signal and the oscillation period of the ring oscillator do not have an equal ratio, a measurement error corresponding to one oscillation period of the ring oscillator may occur even at the application time of the same enable signal. Further, it is difficult to obtain a standard deviation and average of measurement results of performance of the related ring oscillator and a delta value associated with the average. Furthermore, the related measurement apparatus needs a separate register bank or a plurality of flip-flops to set the operating times of a plurality of ring oscillators and set the initial value of a counter for performance measurement, thus increasing the entire chip size.